Do you offer an ASRC IP core, and for which FPGAs?

Yes. Our ASRC IP core is delivered as readable Verilog source. It has been
used on all frontier FPGA vendors.

The licence includes the full source, working examples and functional
simulations. For evaluation we provide a binary module or encrypted source
that runs in a licensed development environment.

Resource use is dominated by DSP slices and block RAM. On small devices such
as the Spartan-6 the configuration may need to be optimised to fit.

Contact us via the support form.